1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having bonding pads for wire bonding.
2. Description of Related Art
In a wafer test, a probe connected to a tester is brought into contact with each pad, to thereby perform a screening process for determining whether a semiconductor chip is defective or non-defective. A semiconductor integrated device has a configuration in which a semiconductor chip is mounted on a substrate and pads formed on the semiconductor chip are connected to stitches (connecting parts), which are formed on the substrate, via bonding wires such as Au wires.
Japanese Unexamined Patent Application Publication No. 2004-63540 (Nakahira) discloses a semiconductor device having a pad of a single-metal-layer structure and a pad of a two-metal-layer structure, which are formed in one pad. FIG. 16 shows the configuration of the semiconductor device disclosed by Nakahira. As shown in FIG. 16, the semiconductor device disclosed by Nakahira has a pad of a two-metal-layer structure (including a first-layer pad 8 and a second-layer pad 1) and a pad 3 of a single-metal-layer structure, which are formed in one pad.
The first-layer pad 8 and the second-layer pad 1 are connected to each other through a plurality of through holes 11. A line 12 for connecting the second-layer pad 1 and the pad 3 of the single-metal-layer structure is formed of a metal wiring layer. The pad 3 of the single-metal-layer structure is used in a wafer test, and the pad of the two-metal-layer structure is used in wire bonding.